Summary
Overview
Work History
Skills
Languages
Traveling , volunteering , cooking, reading
Timeline
Generic

Yulia Goldshtein

Nof Ha Galil

Summary

Accomplished professional with a proven track record at Intel, adept in licenses management. Managing cross site team that leading Electro Magnetic simulation TFM cross geo, optimized IT infrastructure reducing downtime, and delivered innovative layout design solutions. Excels in interpersonal communication and TFM knowledge, driving project success.

Overview

26
26
years of professional experience

Work History

First Line Manager

Intel
05.2022 - Current
  • Managing team inside Analog RF enablement of TEG organization , that leading Electro Magnetic simulation TFM cross geo, cross BU(Business Unit)
  • Established clear objectives for the team, aligning goals with company-wide initiatives for greater impact on business success.
  • Monitored budget expenditures closely, identifying opportunities for cost reduction without sacrificing quality or productivity levels.

DAE(Design Application Engineer) Technical Lead

Intel
05.2019 - 05.2022
  • Exhibited strong technical aptitude and application expertise resulting in optimized performance, continuous improvement recommendations and product innovation.
  • Played a crucial role in successful project completion by contributing technical expertise at all stages of development (analog to BE(backend).
  • Leading all support activities for: tools, setups, environmental and foundry deliverable for WCS projects
  • Generated plan and projection reports to prioritize work.
  • Enhanced the professional ability of the DAE’s team enabling the provision of efficient and effective support across a large range of projects
  • Act as licenses' allocator for WCS

Infrastructure Engineer/DAE and Licenses Allocator

Intel
02.2003 - 05.2019
  • Database management methodology
  • Coordinated with vendors for installation, evaluation, debugging,support
  • Process Design Kit installation, runsets' definition/modification.
  • Deployed and added enhancements for handoff procedure of analog design to integrate into digital top level, conversion of analog Cadence based format into digital Synopsys based files
  • Licenses allocation/optimization and budgeting for WCS includes support and debugging.
  • Developed technical documentation for infrastructure design, implementation, and troubleshooting procedures.
  • Reduced downtime by proactively identifying and addressing potential issues in the IT infrastructure.

Analog Layout Design Engineer

Intel
03.1998 - 02.2003
  • Delivered optimal solutions for complex routing problems through meticulous planning and innovative approaches. Particular example - baseband design (half chip, 90nm)

Skills

Customer Focus

Staff Development

Interpersonal Communication

Layout verification

Licenses management

Skill coding

Shell/Perl coding

Database management

TFM(Tools Flows Methods) knowledge

Languages

Hebrew , Russian
Native language
English
Advanced
C1

Traveling , volunteering , cooking, reading

Love hiking trails

Volunteering in elementary school with children with learning difficulties requires special treatments

Timeline

First Line Manager

Intel
05.2022 - Current

DAE(Design Application Engineer) Technical Lead

Intel
05.2019 - 05.2022

Infrastructure Engineer/DAE and Licenses Allocator

Intel
02.2003 - 05.2019

Analog Layout Design Engineer

Intel
03.1998 - 02.2003

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Yulia Goldshtein