Summary
Overview
Work History
Education
Skills
Languages
Timeline
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Yulia Furmansky

Lead Engineer For Semiconductor Integration And Yield Optimization
Kiryat Gat

Summary

Leading semiconductor manufacturing expert with extensive knowledge in semiconductor processes and a strong focus on process development, transfer, integration, and complex problem-solving. Highly skilled in utilizing advanced data analysis to craft and implement solutions for process yield and performance improvement. Strong interpersonal communicator, capable of fostering teamwork and effectively leading projects to completion without direct authority. Recognized for a solution-oriented, customer-focused approach and a dedicated commitment to driving projects to successful outcomes. A proactive self-learner who leverages a wealth of knowledge and experience to deliver innovative and impactful solutions in the semiconductor field, while consistently maintaining clear, persuasive communication with stakeholders at all levels.

Overview

8
8
years of professional experience

Work History

Senior Integration Technology Leader

Intel
09.2021 - Current
  • Primary Fab-level contact for resolving complex process issues, collaborating with yield and manufacturing teams.
  • Awarded the 2023 Excellence Award for fixing a cross-tech issue, boosting yield and Fab capacity, saving ~$1.6M.
  • Led the transfer and start-up of a novel HBM memory product, collaborating with the development team to optimize front-end processes.
  • Mentored global Intel program at Israel site, that focused on developing leadership skills and personal value for promising female engineers, aimed at enhancing female development and retention.
  • Management the Fab development Silicon (Si) budget, overseeing cost and yield projects, and removing roadblocks for selected initiatives.
  • Led the development of an advanced AI tool for smart trend detection, identifying key parameters for yield and performance improvement, and boosting productivity across multiple Fab teams.

Senior BE&FE Integration Engineer

Intel
02.2019 - 09.2021
  • Coordinated across multiple semiconductor manufacturing groups to ensure the smooth implementation and certification of the new SRAM process within the backend segment.
  • Led key integration roles in the backend (BE) segment, including New Product Introduction (NPI) leadership, collaboration with product and Quality & Reliability (QnR) teams, and worked with US development teams on process improvement projects and their implementation.
  • Transitioned to the front-end segment to address complex technology challenges and production issues following 10nm process ramp-up.
  • Built a robust network with process development peers and gained comprehensive hands-on experience across all manufacturing process segments.
  • Served as Acting Group Leader (GL) for the Backend (BE) Integration group over 6 month period.
  • Led the development of an executive dashboard to effectively track parametric performance across multiple products, achieved with a lean content investment approach.

BE Integration Engineer

Intel
04.2016 - 01.2019
  • Maintenance of process performance and closure of 22nm semiconductor technology within the backend semiconductor processing sector.
  • Temporarily assigned to Intel's Oregon process development site for a four-month period, focusing on the advancement of backend interconnect gap fill processes.
  • Central role in transfer and implementation of 10 nm process technology

Education

Ph.D. - Nanotechnology, Materials Engineering, Chemistry

Ben-Gurion University of The Negev
Beersheba, Israel
04.2001 -

Master of Science - Materials Engineering, Chemistry

Ben-Gurion University of The Negev
Beersheba, Israel
04.2001 -

Bachelor of Science - Chemistry, Biology

Tel-Aviv University
Tel Aviv, Israel
04.2001 -

Skills

Strong Problem-solving abilities

Data Analysis

Complex problems

Data reporting

Semiconductor Manufacturing Processes

Process Integration, Transfer, Optimization

Multitasking

Creative Thinking

Excellent Communication

Project Management

Presentation Skills

Team Collaboration

Languages

Hebrew, Russian
Native language
English
Proficient
C2
German
Elementary
A2

Timeline

Senior Integration Technology Leader

Intel
09.2021 - Current

Senior BE&FE Integration Engineer

Intel
02.2019 - 09.2021

BE Integration Engineer

Intel
04.2016 - 01.2019

Ph.D. - Nanotechnology, Materials Engineering, Chemistry

Ben-Gurion University of The Negev
04.2001 -

Master of Science - Materials Engineering, Chemistry

Ben-Gurion University of The Negev
04.2001 -

Bachelor of Science - Chemistry, Biology

Tel-Aviv University
04.2001 -

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Yulia FurmanskyLead Engineer For Semiconductor Integration And Yield Optimization