Summary
Overview
Work History
Education
Skills
Military Service
Timeline
Generic

Yakir Peretz

VLSI Verification Engineer

Summary

VLSI verification engineer at Chain-Reaction with experience in working on a complex Asic integrating digital and analog design (mixed-signal).

I am hardworking, highly motivated and a fast and independent learner. Interested in Asic and SoC verification,logic design and Chip architecture. Looking for my next challenge where I can harness my abilities and contribute my vast experience, while further expanding my expertise.

Overview

3
3
years of professional experience
7
7
years of post-secondary education

Work History

ADVG Engineer

Chain-Reaction
4 2024 - Current

Define and implement the technology of the Asic independently and in a system as part of the Asic and system bring-up.

  • Define and implement flows in system level and for Asic bring-up
  • Define the next features and architecture for the next Asic generation
  • Embedded coding with C++ (CPP) and python.

VLSI Verification Engineer

Chain-Reaction
11.2021 - 04.2024

Functional and RTL verification of innovative Asics for Bitcoin mining

  • Planning, developing and implementing UVM based verification environments, reference models, tests and testbench for block and full-chip level for digital and mixed-signal designs.
  • Debugging RTL and Verification environment with Xcelium(Simvision and Indago) and Vcs (Verdi).
  • Regression management, run and analysis.
  • CAD - Developing automation tools with Python and CI/CD process on GitHub.

Education

Bachelor of Science - Electrical And Computer Engineering

Ben Gurion University
Israel
05.2017 - 05.2022

Certification - SystemVerilog Accelerated Verification With UVM

Cadence
Israel
08.2022 - 08.2024

Certification - SystemVerilog Accelerated Verification With UVM

Cadence
Israel
08.2022 - 08.2022

Skills

Digital logic verification

Chip and logic design - Plan and design RTL blocks - self projects

SystemVerilog (SV) and OOP

Virtuoso

Python programming and scripts

Git and GitHub

C(CPP) Programming

Verilog

Perl

Unix and Shell scripts

Embedded system

Self and independent learning

Teamwork

Problem solving

Military Service

02-2015 - 11-2016

Combat Support Commander.

  • Supervised over 70 soldiers and officers.
  • Managed unit budgets, logistics facilities and equipment

Timeline

Certification - SystemVerilog Accelerated Verification With UVM

Cadence
08.2022 - 08.2024

Certification - SystemVerilog Accelerated Verification With UVM

Cadence
08.2022 - 08.2022

VLSI Verification Engineer

Chain-Reaction
11.2021 - 04.2024

Bachelor of Science - Electrical And Computer Engineering

Ben Gurion University
05.2017 - 05.2022

ADVG Engineer

Chain-Reaction
4 2024 - Current
Yakir PeretzVLSI Verification Engineer