Tareq Sarhan

Full DLX Processor Implementation (2025)
As part of an advanced digital systems project, I designed and implemented a complete DLX pipelined processor using Verilog. The processor included instruction fetch, decode, execute, memory, and write back stages, along with control logic, hazard detection, and data forwarding mechanisms. I developed a custom instruction set architecture (ISA), wrote assembly programs to test it, and created a Python-based assembler to automate test generation. Functional correctness and timing behavior were validated using Model Sim, and I fine-tuned the pipeline to ensure correct operation under a variety of instruction sequences.

Voltage Regulator with Current Limiting (2025)
For my final project in analog circuit design, I built a robust voltage regulator using a two-stage op-amp architecture with integrated current limiting. The circuit was implemented and simulated in Cadence Virtuoso, focusing on line/load regulation, transient response, and fault protection. I conducted PVT corner analysis, verified the loop stability using Bode plots, and optimized for both accuracy and safety. This project deepened my understanding of analog feedback systems and real-world power delivery challenges.

ALU Design in Virtuoso (2024)
This project involved designing a transistor-level Arithmetic Logic Unit (ALU) using Cadence Virtuoso. I constructed fundamental gates manually, built arithmetic and logic blocks, and verified the operation through schematic and layout simulations. I explored trade-offs between power, area, and delay, and ensured reliable performance through careful sizing and signal routing.

FPGA MAC Unit with FSM Controller (2023)
In this Verilog-based project, I implemented a Multiply-Accumulate (MAC) unit on an FPGA, controlled by a finite state machine. The MAC handled sequential operations with pipeline stages to improve throughput. I wrote automated test benches in Python to verify different operational modes and data dependencies. The project emphasized efficient data path control and synchronization between arithmetic and state-based logic.

Custom Instruction Set CPU Emulator (2025)
To complement my DLX project, I developed a software emulator in C and Python that mimicked the behavior of a simplified custom CPU architecture. This included memory-mapped I/O, register files, and support for arithmetic, branching, and control flow. The emulator enabled rapid prototyping of assembly programs and provided insight into instruction-level simulation, debugging, and performance profiling.