Or Langer

• Ownership of up to 3 blocks in CPU chips, from PnR to signoff.

• Hierarchical blocks verification - STA, PDV, EM & IR.

• Collaborating with other groups around the world.

• Mentoring students.

• Ownership of hierarchical CPU partition, includes PnR & physical verification & STA.

• Developing the top level flow - boxes allocation, pin assignment & top PG mesh.

• Full ownership of up to 5 blocks in high speed networking chips.

• Responsibility from synthesis to PD verification: PDV, STA, LEQ, EM, IR.
• Close collaboration with the RTL design team.

• Flow optimization.

• Floorplanning with block diagrams & schematics.