Mit Pankajkumar Patel

Detail-oriented entry-level professional skilled in software development and data analysis. Leverages strong time management and organizational skills to enhance operations and drive company growth. Focused on delivering results through effective collaboration and innovative problem-solving.

• Supply Connect, This web application is easy to use and will reduce the paper used in the recurring system for the keeping information of client. There is no headache of remembering or storing of the paper work of the old and new client. Thus, we can conclude that we can give order through Online or as User Manual. We can also either purchase it. We can specialize issue material through online., Java Script, JQuery, JSP Servlet
• S-Assistant, The purpose of developing attendance app is to mobilize the traditional way of taking attendance. Using this android app, a teacher can take attendance using any android mobile phone. Using this app, teacher can add profiles of students for classes., Java Development Kit, Android SDK, Android Studio
• Design of Computing Accelerator for Digital Data using Hardware-Software Approach, ZYNQ PS-PL interfacing provides rich set of interfaces where low, moderate and high data rates are supported as well as memory mapped interface with and without addressing modes are also supported. Data rate and bandwidth requirement justifies the need of application. For low bandwidth applications GP port is found to be suitable, but for high speed applications High Performance (HP) port and Accelerator Coherence Port (ACP) performs better. However, both port have advantages as well as disadvantages. ACP port has advantages of coherency for cache memory. For certain data processing application due to coherency processor will consume less power and can have high performance compare to HP port. However, if any other computing task has higher priority, performance may have degraded due to such coherent entry in L2 cache. In such case HP port is better since it provides same performance for data transfer in DDR memory as ACP port supports., Vivado, Xilinx ISE, Xilinx SDK, FPGA, ZedBoard

• English
• Hindi
• Gujarati

• Date of Birth: 08/08/1994
• Gender: Male
• Nationality: India
• Marital Status: Married