Michael Michaeli

• Managing a digital design team of 5 engineers, providing technical leadership, guidance, and ensuring successful project execution.
• Contributed to the chip-level architecture, actively involved in high-level design discussions and cross-functional collaboration.
• Performed RTL and gate-level power estimation using tools such as Power Artist and PrimeTime PX utilizing FSDB and SAIF switching activity files to ensure accurate analysis; supported low-power design techniques including clock gating and power domain implementation.

• Complex ASIC modules development for image processing algorithms for Samsung galaxy cameras.
• Verilog based, power efficient logic design and integration for high performance parallel image processing.
• Proficiency in documentation, implementing and simulating designs.
  Participated in design reviews and created design documentation.
• Tutor new employees and guide them through their tasks.

Teaching assistant at the Faculty of Engineering.

• Check and evaluate student assignments.

• Guide the students during the courses.